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<!@TC:1520378962>
#Build: Synplify Pro L-2016.09L, Build 077R, Dec  2 2016
#install: C:\lscc\diamond\3.9_x64\synpbase
#OS: Windows 8 6.2
#Hostname: DESKTOP-V34NFE6

# Tue Mar 06 15:29:22 2018

#Implementation: impl

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1520378963> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1520378963> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.v" (library work)
@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.9_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\bootloader.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\edge_detect.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\tinyfpga_bootloader.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_arb.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_arb.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_pe.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_rx.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx_mux.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_reset_det.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v" (library work)
@I::"C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\source\usb_pll_inst.v" (library work)
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module TinyFPGA_EX
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.v:757:7:757:10:@N:CG364:@XP_MSG">ecp5u.v(757)</a><!@TM:1520378963> | Synthesizing module VHI in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.v:761:7:761:10:@N:CG364:@XP_MSG">ecp5u.v(761)</a><!@TM:1520378963> | Synthesizing module VLO in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.v:1696:7:1696:14:@N:CG364:@XP_MSG">ecp5u.v(1696)</a><!@TM:1520378963> | Synthesizing module EHXPLLL in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\source\usb_pll_inst.v:8:7:8:19:@N:CG364:@XP_MSG">usb_pll_inst.v(8)</a><!@TM:1520378963> | Synthesizing module usb_pll_inst in library work.

<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\source\usb_pll_inst.v:18:8:18:22:@W:CL168:@XP_MSG">usb_pll_inst.v(18)</a><!@TM:1520378963> | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\edge_detect.v:1:7:1:27:@N:CG364:@XP_MSG">edge_detect.v(1)</a><!@TM:1520378963> | Synthesizing module rising_edge_detector in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\edge_detect.v:15:7:15:28:@N:CG364:@XP_MSG">edge_detect.v(15)</a><!@TM:1520378963> | Synthesizing module falling_edge_detector in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:1:7:1:25:@N:CG364:@XP_MSG">usb_serial_ctrl_ep.v(1)</a><!@TM:1520378963> | Synthesizing module usb_serial_ctrl_ep in library work.

<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:15:9:15:21:@W:CG360:@XP_MSG">usb_serial_ctrl_ep.v(15)</a><!@TM:1520378963> | Removing wire out_ep_stall, as there is no assignment to it.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL169:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused register raw_setup_data[5][9:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL169:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused register raw_setup_data[4][9:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 8 of raw_setup_data[7][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 8 of raw_setup_data[6][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 8 of raw_setup_data[3][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 7 of raw_setup_data[2][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 8 of raw_setup_data[1][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 9 to 8 of raw_setup_data[0][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning unused bits 6 to 0 of raw_setup_data[0][9:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:CL189:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Register bit rom_length[3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:CL189:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Register bit rom_length[5] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL260:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning register bit 5 of rom_length[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL260:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning register bit 3 of rom_length[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:1:7:1:24:@N:CG364:@XP_MSG">usb_spi_bridge_ep.v(1)</a><!@TM:1520378963> | Synthesizing module usb_spi_bridge_ep in library work.

<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:15:9:15:21:@W:CG360:@XP_MSG">usb_spi_bridge_ep.v(15)</a><!@TM:1520378963> | Removing wire out_ep_stall, as there is no assignment to it.</font>
<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:28:9:28:20:@W:CG360:@XP_MSG">usb_spi_bridge_ep.v(28)</a><!@TM:1520378963> | Removing wire in_ep_stall, as there is no assignment to it.</font>
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:391:2:391:8:@W:CL265:@XP_MSG">usb_spi_bridge_ep.v(391)</a><!@TM:1520378963> | Removing unused bit 8 of spi_in_data[8:0]. Either assign all bits or reduce the width of the signal.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[31]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[31]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[30]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[30]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[29]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[29]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[28]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[28]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[27]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[27]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[26]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[26]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[25]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[25]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[24]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[24]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[23]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[23]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[22]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[22]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[21]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[21]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[20]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[20]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[19]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[19]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[18]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[18]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[17]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[17]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[16]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[16]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[15]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[15]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[14]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[14]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[13]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[13]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[12]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[12]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[11]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[11]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[10]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[10]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[9]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[9]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[8]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[8]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[7]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[7]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[6]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[6]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[5]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[5]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[4]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[4]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[3]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[3]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[2]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[2]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[1]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[1]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_values[0]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@W:CL118:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378963> | Latch generated from always block for signal output_pin_enables[0]; possible missing assignment in an if or case statement.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_arb.v:1:7:1:20:@N:CG364:@XP_MSG">usb_fs_in_arb.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_in_arb in library work.

	NUM_IN_EPS=5'b00011
   Generated name = usb_fs_in_arb_3

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_arb.v:1:7:1:21:@N:CG364:@XP_MSG">usb_fs_out_arb.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_out_arb in library work.

	NUM_OUT_EPS=5'b00010
   Generated name = usb_fs_out_arb_2

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:2:7:2:19:@N:CG364:@XP_MSG">usb_fs_in_pe.v(2)</a><!@TM:1520378963> | Synthesizing module usb_fs_in_pe in library work.

	NUM_IN_EPS=5'b00011
	MAX_IN_PACKET_SIZE=32'b00000000000000000000000000100000
	READY_FOR_PKT=32'b00000000000000000000000000000000
	PUTTING_PKT=32'b00000000000000000000000000000001
	GETTING_PKT=32'b00000000000000000000000000000010
	STALL=32'b00000000000000000000000000000011
	IDLE=32'b00000000000000000000000000000000
	RCVD_IN=32'b00000000000000000000000000000001
	SEND_DATA=32'b00000000000000000000000000000010
	WAIT_ACK=32'b00000000000000000000000000000011
   Generated name = usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s

<font color=#A52A2A>@W:<a href="@W:CG532:@XP_HELP">CG532</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:100:2:100:9:@W:CG532:@XP_MSG">usb_fs_in_pe.v(100)</a><!@TM:1520378963> | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.</font>
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:261:2:261:8:@N:CL134:@XP_MSG">usb_fs_in_pe.v(261)</a><!@TM:1520378963> | Found RAM in_data_buffer, depth=96, width=8
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:284:4:284:8:@W:CL118:@XP_MSG">usb_fs_in_pe.v(284)</a><!@TM:1520378963> | Latch generated from always block for signal tx_pid[3:0]; possible missing assignment in an if or case statement.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:CL189:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378963> | Register bit current_endp[2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:CL189:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378963> | Register bit current_endp[3] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:347:2:347:8:@W:CL279:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378963> | Pruning register bits 3 to 2 of current_endp[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:2:7:2:20:@N:CG364:@XP_MSG">usb_fs_out_pe.v(2)</a><!@TM:1520378963> | Synthesizing module usb_fs_out_pe in library work.

	NUM_OUT_EPS=5'b00010
	MAX_OUT_PACKET_SIZE=32'b00000000000000000000000000100000
	READY_FOR_PKT=32'b00000000000000000000000000000000
	PUTTING_PKT=32'b00000000000000000000000000000001
	GETTING_PKT=32'b00000000000000000000000000000010
	STALL=32'b00000000000000000000000000000011
	IDLE=32'b00000000000000000000000000000000
	RCVD_OUT=32'b00000000000000000000000000000001
	RCVD_DATA_START=32'b00000000000000000000000000000010
	RCVD_DATA_END=32'b00000000000000000000000000000011
   Generated name = usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s

<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@W:CL169:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Pruning unused register last_data_toggle. Make sure that there are no unused intermediate registers.</font>
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:CL134:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Found RAM out_data_buffer, depth=64, width=8
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:282:4:282:8:@W:CL118:@XP_MSG">usb_fs_out_pe.v(282)</a><!@TM:1520378963> | Latch generated from always block for signal out_ep_acked[1]; possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL118:@XP_HELP">CL118</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:282:4:282:8:@W:CL118:@XP_MSG">usb_fs_out_pe.v(282)</a><!@TM:1520378963> | Latch generated from always block for signal out_ep_acked[0]; possible missing assignment in an if or case statement.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:CL189:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Register bit current_endp[1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:CL189:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Register bit current_endp[2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:CL189:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Register bit current_endp[3] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@W:CL279:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Pruning register bits 3 to 1 of current_endp[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_rx.v:1:7:1:16:@N:CG364:@XP_MSG">usb_fs_rx.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_rx in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx_mux.v:1:7:1:20:@N:CG364:@XP_MSG">usb_fs_tx_mux.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_tx_mux in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:1:7:1:16:@N:CG364:@XP_MSG">usb_fs_tx.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_tx in library work.

@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL189:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Register bit se0_shift_reg[7] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@W:CL260:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Pruning register bit 7 of se0_shift_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_pe.v:1:7:1:16:@N:CG364:@XP_MSG">usb_fs_pe.v(1)</a><!@TM:1520378963> | Synthesizing module usb_fs_pe in library work.

	NUM_OUT_EPS=5'b00010
	NUM_IN_EPS=5'b00011
   Generated name = usb_fs_pe_2_3

<font color=#A52A2A>@W:<a href="@W:CG781:@XP_HELP">CG781</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_pe.v:124:4:124:21:@W:CG781:@XP_MSG">usb_fs_pe.v(124)</a><!@TM:1520378963> | Input reset_ep on instance usb_fs_in_pe_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. </font>
<font color=#A52A2A>@W:<a href="@W:CG781:@XP_HELP">CG781</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_pe.v:157:4:157:22:@W:CG781:@XP_MSG">usb_fs_pe.v(157)</a><!@TM:1520378963> | Input reset_ep on instance usb_fs_out_pe_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. </font>
<font color=#A52A2A>@W:<a href="@W:CG781:@XP_HELP">CG781</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_pe.v:157:4:157:22:@W:CG781:@XP_MSG">usb_fs_pe.v(157)</a><!@TM:1520378963> | Input bit_strobe on instance usb_fs_out_pe_inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. </font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\tinyfpga_bootloader.v:1:7:1:26:@N:CG364:@XP_MSG">tinyfpga_bootloader.v(1)</a><!@TM:1520378963> | Synthesizing module tinyfpga_bootloader in library work.

<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\tinyfpga_bootloader.v:61:2:61:8:@W:CL169:@XP_MSG">tinyfpga_bootloader.v(61)</a><!@TM:1520378963> | Pruning unused register ms_cnt[9:0]. Make sure that there are no unused intermediate registers.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.v:1591:7:1591:14:@N:CG364:@XP_MSG">ecp5u.v(1591)</a><!@TM:1520378963> | Synthesizing module USRMCLK in library work.

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\bootloader.v:1:7:1:18:@N:CG364:@XP_MSG">bootloader.v(1)</a><!@TM:1520378963> | Synthesizing module TinyFPGA_EX in library work.

@N:<a href="@N:CL135:@XP_HELP">CL135</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:61:2:61:8:@N:CL135:@XP_MSG">usb_fs_tx.v(61)</a><!@TM:1520378963> | Found sequential shift bitstuff_qqqq with address depth of 4 words and data bit width of 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL189:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Register bit se0_shift_reg[6] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@W:CL260:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Pruning register bit 6 of se0_shift_reg[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL189:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Register bit se0_shift_reg[5] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@W:CL260:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Pruning register bit 5 of se0_shift_reg[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL189:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Register bit se0_shift_reg[4] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@W:CL260:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Pruning register bit 4 of se0_shift_reg[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL201:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Trying to extract state machine for register pkt_state.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@N:CL189:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Register bit se0_shift_reg[3] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:82:2:82:8:@W:CL260:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378963> | Pruning register bit 3 of se0_shift_reg[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_tx.v:5:8:5:13:@N:CL159:@XP_MSG">usb_fs_tx.v(5)</a><!@TM:1520378963> | Input reset is unused.
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_rx.v:81:2:81:8:@N:CL201:@XP_MSG">usb_fs_rx.v(81)</a><!@TM:1520378963> | Trying to extract state machine for register line_state.
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:CL201:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378963> | Trying to extract state machine for register genblk1[1].ep_state_1_.
Extracted state machine for register genblk1[1].ep_state_1_
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:CL201:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378963> | Trying to extract state machine for register genblk1[0].ep_state_0_.
Extracted state machine for register genblk1[0].ep_state_0_
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:CL201:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Trying to extract state machine for register out_xfr_state.
Extracted state machine for register out_xfr_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
<font color=#A52A2A>@W:<a href="@W:CL249:@XP_HELP">CL249</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:354:2:354:8:@W:CL249:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378963> | Initial value is not supported on state machine out_xfr_state</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:10:8:10:18:@N:CL159:@XP_MSG">usb_fs_out_pe.v(10)</a><!@TM:1520378963> | Input bit_strobe is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:36:15:36:27:@N:CL159:@XP_MSG">usb_fs_out_pe.v(36)</a><!@TM:1520378963> | Input rx_frame_num is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_out_pe.v:49:8:49:18:@N:CL159:@XP_MSG">usb_fs_out_pe.v(49)</a><!@TM:1520378963> | Input tx_pkt_end is unused.
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:CL201:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378963> | Trying to extract state machine for register genblk1[2].ep_state_2_.
Extracted state machine for register genblk1[2].ep_state_2_
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:CL201:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378963> | Trying to extract state machine for register genblk1[1].ep_state_1_.
Extracted state machine for register genblk1[1].ep_state_1_
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:CL201:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378963> | Trying to extract state machine for register genblk1[0].ep_state_0_.
Extracted state machine for register genblk1[0].ep_state_0_
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:CL201:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378963> | Trying to extract state machine for register in_xfr_state.
Extracted state machine for register in_xfr_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
<font color=#A52A2A>@W:<a href="@W:CL249:@XP_HELP">CL249</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:347:2:347:8:@W:CL249:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378963> | Initial value is not supported on state machine in_xfr_state</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:28:8:28:20:@N:CL159:@XP_MSG">usb_fs_in_pe.v(28)</a><!@TM:1520378963> | Input rx_pkt_start is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:36:15:36:27:@N:CL159:@XP_MSG">usb_fs_in_pe.v(36)</a><!@TM:1520378963> | Input rx_frame_num is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_fs_in_pe.v:45:8:45:18:@N:CL159:@XP_MSG">usb_fs_in_pe.v(45)</a><!@TM:1520378963> | Input tx_pkt_end is unused.
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:391:2:391:8:@N:CL201:@XP_MSG">usb_spi_bridge_ep.v(391)</a><!@TM:1520378963> | Trying to extract state machine for register spi_state.
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:256:2:256:8:@N:CL201:@XP_MSG">usb_spi_bridge_ep.v(256)</a><!@TM:1520378963> | Trying to extract state machine for register cmd_state.
<font color=#A52A2A>@W:<a href="@W:CL157:@XP_HELP">CL157</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:15:9:15:21:@W:CL157:@XP_MSG">usb_spi_bridge_ep.v(15)</a><!@TM:1520378963> | *Output out_ep_stall has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.</font>
<font color=#A52A2A>@W:<a href="@W:CL157:@XP_HELP">CL157</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:28:9:28:20:@W:CL157:@XP_MSG">usb_spi_bridge_ep.v(28)</a><!@TM:1520378963> | *Output in_ep_stall has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.</font>
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:3:8:3:13:@N:CL159:@XP_MSG">usb_spi_bridge_ep.v(3)</a><!@TM:1520378963> | Input reset is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:12:8:12:20:@N:CL159:@XP_MSG">usb_spi_bridge_ep.v(12)</a><!@TM:1520378963> | Input out_ep_setup is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:16:8:16:20:@N:CL159:@XP_MSG">usb_spi_bridge_ep.v(16)</a><!@TM:1520378963> | Input out_ep_acked is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_spi_bridge_ep.v:29:8:29:19:@N:CL159:@XP_MSG">usb_spi_bridge_ep.v(29)</a><!@TM:1520378963> | Input in_ep_acked is unused.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:CL189:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Register bit bytes_sent[7] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@W:CL260:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378963> | Pruning register bit 7 of bytes_sent[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:216:2:216:8:@N:CL201:@XP_MSG">usb_serial_ctrl_ep.v(216)</a><!@TM:1520378963> | Trying to extract state machine for register ctrl_xfr_state.
Extracted state machine for register ctrl_xfr_state
State machine has 6 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
<font color=#A52A2A>@W:<a href="@W:CL249:@XP_HELP">CL249</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:216:2:216:8:@W:CL249:@XP_MSG">usb_serial_ctrl_ep.v(216)</a><!@TM:1520378963> | Initial value is not supported on state machine ctrl_xfr_state</font>
<font color=#A52A2A>@W:<a href="@W:CL157:@XP_HELP">CL157</a> : <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\common\usb_serial_ctrl_ep.v:15:9:15:21:@W:CL157:@XP_MSG">usb_serial_ctrl_ep.v(15)</a><!@TM:1520378963> | *Output out_ep_stall has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.</font>

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Mar 06 15:29:23 2018

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1520378963> | Running in 64-bit mode 

Linker output is up to date. No re-linking necessary


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Mar 06 15:29:23 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Mar 06 15:29:23 2018

###########################################################]

@A: : <!@TM:1520378963> | multi_srs_gen output is up to date. No run necessary. 
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Multi-srs Generator Report
<a name=compilerReport4_head></a>Linked File: <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\synlog\diamond_impl_multi_srs_gen.srr:@XP_FILE">diamond_impl_multi_srs_gen.srr</a>
Pre-mapping Report

# Tue Mar 06 15:29:23 2018

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 10:33:02</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1520378964> | No constraint file specified. 
Linked File: <a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl_scck.rpt:@XP_FILE">diamond_impl_scck.rpt</a>
Printing clock  summary report in "C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1520378964> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1520378964> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 117MB)

<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1520378964> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 
@A:<a href="@A:FX681:@XP_HELP">FX681</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_tx.v:82:2:82:8:@A:FX681:@XP_MSG">usb_fs_tx.v(82)</a><!@TM:1520378964> | Initial value on register bit_count[2:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[0] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[1] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[2] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[3] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[4] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[5] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[6] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[7] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.endp[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[8] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.endp[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:332:2:332:8:@W:BN132:@XP_MSG">usb_fs_rx.v(332)</a><!@TM:1520378964> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.frame_num[9] because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.endp[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:15:9:15:21:@N:MO111:@XP_MSG">usb_serial_ctrl_ep.v(15)</a><!@TM:1520378964> | Tristate driver out_ep_stall (in view: work.usb_serial_ctrl_ep(verilog)) on net out_ep_stall (in view: work.usb_serial_ctrl_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:28:9:28:20:@N:MO111:@XP_MSG">usb_spi_bridge_ep.v(28)</a><!@TM:1520378964> | Tristate driver in_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) on net in_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:15:9:15:21:@N:MO111:@XP_MSG">usb_spi_bridge_ep.v(15)</a><!@TM:1520378964> | Tristate driver out_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) on net out_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[0] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[1] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[2] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[3] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[4] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[5] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[6] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[7] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[8] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[9] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[10] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[11] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[12] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[13] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[14] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[15] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[16] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[17] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[18] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[19] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[20] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[21] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[22] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[23] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[24] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[25] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[26] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[27] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[28] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[29] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[30] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_values_1[31] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[0] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[1] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[2] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[3] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[4] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[5] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[6] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[7] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[8] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[9] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[10] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[11] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[12] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[13] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[14] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[15] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[16] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[17] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[18] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[19] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[20] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[21] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[22] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[23] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[24] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[25] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[26] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[27] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[28] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[29] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[30] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:151:4:151:8:@N:BN362:@XP_MSG">usb_spi_bridge_ep.v(151)</a><!@TM:1520378964> | Removing sequential instance output_pin_enables_1[31] (in view: work.usb_spi_bridge_ep(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:282:4:282:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(282)</a><!@TM:1520378964> | Removing sequential instance out_ep_acked_1[1] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)) of type view:PrimLib.latr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:239:2:239:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(239)</a><!@TM:1520378964> | Removing sequential instance out_ep_setup[1] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=108  set on top level netlist TinyFPGA_EX

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)



<a name=mapperReport6></a>Clock Summary</a>
*****************

Start                                                                        Requested     Requested     Clock                                                Clock                     Clock
Clock                                                                        Frequency     Period        Type                                                 Group                     Load 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                       1.0 MHz       1000.000      system                                               system_clkgroup           1    
TinyFPGA_EX|pin_clk                                                          927.5 MHz     1.078         inferred                                             Autoconstr_clkgroup_0     10   
usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s|in_xfr_state_derived_clock[1]     4.2 MHz       240.282       derived (from usb_pll_inst|CLKOP_inferred_clock)     Autoconstr_clkgroup_1     67   
usb_pll_inst|CLKOP_inferred_clock                                            4.2 MHz       240.282       inferred                                             Autoconstr_clkgroup_1     527  
=============================================================================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT531:@XP_HELP">MT531</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:282:4:282:8:@W:MT531:@XP_MSG">usb_fs_out_pe.v(282)</a><!@TM:1520378964> | Found signal identified as System clock which controls 1 sequential elements including tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_ep_acked_1[0].  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\boards\tinyfpga_ex\bootloader.v:79:2:79:8:@W:MT529:@XP_MSG">bootloader.v(79)</a><!@TM:1520378964> | Found inferred clock TinyFPGA_EX|pin_clk which controls 10 sequential elements including initiate_boot. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\edge_detect.v:8:2:8:8:@W:MT529:@XP_MSG">edge_detect.v(8)</a><!@TM:1520378964> | Found inferred clock usb_pll_inst|CLKOP_inferred_clock which controls 527 sequential elements including tinyfpga_bootloader_inst.ctrl_ep_inst.detect_pkt_start.in_q. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

Encoding state machine ctrl_xfr_state[5:0] (in view: work.usb_serial_ctrl_ep(verilog))
original code -> new code
   000000 -> 000001
   000001 -> 000010
   000010 -> 000100
   000011 -> 001000
   000100 -> 010000
   000101 -> 100000
Encoding state machine genblk1\[2\]\.ep_state_2_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378964> | There are no possible illegal states for state machine genblk1\[2\]\.ep_state_2_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378964> | There are no possible illegal states for state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378964> | There are no possible illegal states for state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine in_xfr_state[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:MO225:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378964> | There are no possible illegal states for state machine in_xfr_state[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:MO225:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378964> | There are no possible illegal states for state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:MO225:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378964> | There are no possible illegal states for state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine out_xfr_state[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:MO225:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378964> | There are no possible illegal states for state machine out_xfr_state[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 145MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Mar 06 15:29:24 2018

###########################################################]
Map & Optimize Report

# Tue Mar 06 15:29:24 2018

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec  5 2016 10:33:02</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1520378969> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1520378969> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)

@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:15:9:15:21:@N:MO111:@XP_MSG">usb_serial_ctrl_ep.v(15)</a><!@TM:1520378969> | Tristate driver out_ep_stall (in view: work.usb_serial_ctrl_ep(verilog)) on net out_ep_stall (in view: work.usb_serial_ctrl_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:28:9:28:20:@N:MO111:@XP_MSG">usb_spi_bridge_ep.v(28)</a><!@TM:1520378969> | Tristate driver in_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) on net in_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:15:9:15:21:@N:MO111:@XP_MSG">usb_spi_bridge_ep.v(15)</a><!@TM:1520378969> | Tristate driver out_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) on net out_ep_stall (in view: work.usb_spi_bridge_ep(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <!@TM:1520378969> | Tristate driver ctrl_out_ep_stall_t (in view: work.tinyfpga_bootloader(verilog)) on net ctrl_out_ep_stall (in view: work.tinyfpga_bootloader(verilog)) has its enable tied to GND. 
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <!@TM:1520378969> | Tristate driver serial_out_ep_stall_t (in view: work.tinyfpga_bootloader(verilog)) on net serial_out_ep_stall (in view: work.tinyfpga_bootloader(verilog)) has its enable tied to GND. 
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <!@TM:1520378969> | Tristate driver serial_in_ep_stall_t (in view: work.tinyfpga_bootloader(verilog)) on net serial_in_ep_stall (in view: work.tinyfpga_bootloader(verilog)) has its enable tied to GND. 
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\edge_detect.v:8:2:8:8:@W:BN132:@XP_MSG">edge_detect.v(8)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.ctrl_ep_inst.detect_pkt_start.in_q because it is equivalent to instance tinyfpga_bootloader_inst.ctrl_ep_inst.detect_pkt_end.in_q. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>

Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1520378969> | Auto Constrain mode is enabled 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000000" on instance tinyfpga_bootloader_inst.ctrl_ep_inst.new_dev_addr[6:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.ctrl_ep_inst.rom_length[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000000" on instance tinyfpga_bootloader_inst.ctrl_ep_inst.dev_addr_i[6:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_spi_bridge_ep_inst.spi_state[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000" on instance tinyfpga_bootloader_inst.usb_spi_bridge_ep_inst.cmd_state[3:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000000" on instance tinyfpga_bootloader_inst.usb_spi_bridge_ep_inst.spi_out_data[8:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000000" on instance tinyfpga_bootloader_inst.usb_spi_bridge_ep_inst.spi_in_data[7:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.data_toggle[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid[3:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_ep_setup[1:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.data_toggle[1:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.rx_data_buffer[8:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.endp[3:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.addr[6:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.token_payload[11:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000000000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.crc16[15:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.crc5[4:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.full_pid[8:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.line_state[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.dpair_q[3:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.bitstuff_history[5:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.line_history[5:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[7:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000000000000000000000000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state[31:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.se0_shift_reg[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.oe_shift_reg[7:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000000000000000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.crc16[15:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "0000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pidq[3:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.dp_eop[2:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "00000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.bit_history_q[4:0]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1520378969> | Applying initial value "000" on instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.bit_count[2:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)

@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\boards\tinyfpga_ex\bootloader.v:79:2:79:8:@N:MO231:@XP_MSG">bootloader.v(79)</a><!@TM:1520378969> | Found counter in view:work.TinyFPGA_EX(verilog) instance boot_delay[8:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\tinyfpga_bootloader.v:87:2:87:8:@N:MO231:@XP_MSG">tinyfpga_bootloader.v(87)</a><!@TM:1520378969> | Found counter in view:work.tinyfpga_bootloader(verilog) instance pwm_cnt[7:0] 
Encoding state machine ctrl_xfr_state[5:0] (in view: work.usb_serial_ctrl_ep(verilog))
original code -> new code
   000000 -> 000001
   000001 -> 000010
   000010 -> 000100
   000011 -> 001000
   000100 -> 010000
   000101 -> 100000
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:MO231:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Found counter in view:work.usb_serial_ctrl_ep(verilog) instance rom_addr[6:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:256:2:256:8:@N:MO231:@XP_MSG">usb_spi_bridge_ep.v(256)</a><!@TM:1520378969> | Found counter in view:work.usb_spi_bridge_ep(verilog) instance data_out_length[15:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_spi_bridge_ep.v:256:2:256:8:@N:MO231:@XP_MSG">usb_spi_bridge_ep.v(256)</a><!@TM:1520378969> | Found counter in view:work.usb_spi_bridge_ep(verilog) instance data_in_length[15:0] 
Encoding state machine genblk1\[2\]\.ep_state_2_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | There are no possible illegal states for state machine genblk1\[2\]\.ep_state_2_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | There are no possible illegal states for state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@N:MO225:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | There are no possible illegal states for state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine in_xfr_state[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:MO225:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378969> | There are no possible illegal states for state machine in_xfr_state[3:0] (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:124:4:124:25:@N:MF179:@XP_MSG">usb_fs_in_pe.v(124)</a><!@TM:1520378969> | Found 7 by 7 bit equality operator ('==') un1_dev_addr (in view: work.usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
Encoding state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:MO225:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378969> | There are no possible illegal states for state machine genblk1\[1\]\.ep_state_1_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:MO225:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378969> | There are no possible illegal states for state machine genblk1\[0\]\.ep_state_0_[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine out_xfr_state[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:MO225:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | There are no possible illegal states for state machine out_xfr_state[3:0] (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N:<a href="@N:MF179:@XP_HELP">MF179</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:116:4:116:25:@N:MF179:@XP_MSG">usb_fs_out_pe.v(116)</a><!@TM:1520378969> | Found 7 by 7 bit equality operator ('==') un1_dev_addr (in view: work.usb_fs_out_pe_2_32s_0s_1s_2s_3s_0s_1s_2s_3s(verilog))

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 157MB)

@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:BN362:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.genblk1\[0\]\.ep_state_0_[1] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:218:6:218:12:@N:BN362:@XP_MSG">usb_fs_out_pe.v(218)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.genblk1\[0\]\.ep_state_0_[0] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_xfr_state[1] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_xfr_state[0] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.current_endp[0] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:BN362:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.nak_out_transfer (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_xfr_state[1] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_xfr_state[0] (in view: work.TinyFPGA_EX(verilog)) because it does not drive other instances.

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 158MB)

@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:284:4:284:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(284)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid[3] (in view: work.TinyFPGA_EX(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:284:4:284:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(284)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid[2] (in view: work.TinyFPGA_EX(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:284:4:284:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(284)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid[1] (in view: work.TinyFPGA_EX(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:284:4:284:8:@N:BN362:@XP_MSG">usb_fs_in_pe.v(284)</a><!@TM:1520378969> | Removing sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid[0] (in view: work.TinyFPGA_EX(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 158MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 158MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 158MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 158MB)

@N:<a href="@N:FO126:@XP_HELP">FO126</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:261:2:261:8:@N:FO126:@XP_MSG">usb_fs_in_pe.v(261)</a><!@TM:1520378969> | Generating RAM tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer[7:0]
@N:<a href="@N:FO126:@XP_HELP">FO126</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:FO126:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Generating RAM tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_data_buffer[7:0]
@N:<a href="@N:FX214:@XP_HELP">FX214</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:338:4:338:8:@N:FX214:@XP_MSG">usb_serial_ctrl_ep.v(338)</a><!@TM:1520378969> | Generating ROM tinyfpga_bootloader_inst.ctrl_ep_inst.in_ep_data_1[7:0] (in view: work.TinyFPGA_EX(verilog)).
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:261:2:261:8:@W:BN132:@XP_MSG">usb_fs_in_pe.v(261)</a><!@TM:1520378969> | Removing black box instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer_ram_9 because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer_ram_7. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:261:2:261:8:@W:BN132:@XP_MSG">usb_fs_in_pe.v(261)</a><!@TM:1520378969> | Removing black box instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer_ram_8 because it is equivalent to instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.in_data_buffer_ram_10. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>

Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 158MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 180MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -2.36ns		 827 /       504
   2		0h:00m:02s		    -2.36ns		 823 /       504
   3		0h:00m:02s		    -2.36ns		 825 /       504
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:135:4:135:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(135)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.status_stage_end_iv (in view: work.TinyFPGA_EX(verilog)) with 15 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.bytes_sent[0] (in view: work.TinyFPGA_EX(verilog)) with 6 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.bytes_sent[2] (in view: work.TinyFPGA_EX(verilog)) with 6 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.bytes_sent[1] (in view: work.TinyFPGA_EX(verilog)) with 6 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:FX271:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.ep_put_addr\[0\][1] (in view: work.TinyFPGA_EX(verilog)) with 7 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:FX271:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.ep_put_addr\[0\][2] (in view: work.TinyFPGA_EX(verilog)) with 5 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:277:2:277:8:@N:FX271:@XP_MSG">usb_fs_rx.v(277)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.crc16[15] (in view: work.TinyFPGA_EX(verilog)) with 4 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.bytes_sent[4] (in view: work.TinyFPGA_EX(verilog)) with 5 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_serial_ctrl_ep.v:224:2:224:8:@N:FX271:@XP_MSG">usb_serial_ctrl_ep.v(224)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.ctrl_ep_inst.bytes_sent[3] (in view: work.TinyFPGA_EX(verilog)) with 6 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:240:2:240:8:@N:FX271:@XP_MSG">usb_fs_rx.v(240)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.full_pid[1] (in view: work.TinyFPGA_EX(verilog)) with 22 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:240:2:240:8:@N:FX271:@XP_MSG">usb_fs_rx.v(240)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.full_pid[2] (in view: work.TinyFPGA_EX(verilog)) with 24 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:354:2:354:8:@N:FX271:@XP_MSG">usb_fs_out_pe.v(354)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.ep_put_addr\[0\][3] (in view: work.TinyFPGA_EX(verilog)) with 4 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_rx.v:240:2:240:8:@N:FX271:@XP_MSG">usb_fs_rx.v(240)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_rx_inst.full_pid[4] (in view: work.TinyFPGA_EX(verilog)) with 15 loads 1 time to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:FX271:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp[0] (in view: work.TinyFPGA_EX(verilog)) with 33 loads 3 times to improve timing.
Timing driven replication report
Added 17 Registers via timing driven replication
Added 15 LUTs via timing driven replication

   4		0h:00m:03s		    -1.92ns		 861 /       521
   5		0h:00m:03s		    -1.81ns		 862 /       521
   6		0h:00m:03s		    -1.60ns		 864 /       521
   7		0h:00m:03s		    -1.60ns		 866 /       521
   8		0h:00m:03s		    -1.49ns		 867 /       521
   9		0h:00m:03s		    -1.43ns		 868 /       521
  10		0h:00m:03s		    -1.43ns		 870 /       521
  11		0h:00m:03s		    -1.43ns		 871 /       521
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:347:2:347:8:@N:FX271:@XP_MSG">usb_fs_in_pe.v(347)</a><!@TM:1520378969> | Replicating instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp[1] (in view: work.TinyFPGA_EX(verilog)) with 32 loads 3 times to improve timing.
Added 3 Registers via timing driven replication
Added 3 LUTs via timing driven replication


  12		0h:00m:03s		    -1.43ns		 873 /       524
  13		0h:00m:03s		    -1.36ns		 875 /       524
  14		0h:00m:03s		    -1.28ns		 876 /       524

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 180MB)

<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1520378969> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1520378969> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_out_pe.v:282:4:282:8:@W:MO129:@XP_MSG">usb_fs_out_pe.v(282)</a><!@TM:1520378969> | Sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_out_pe_inst.out_ep_acked_1[0] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO160:@XP_HELP">MO160</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@W:MO160:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | Register bit tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.genblk1\[2\]\.ep_state_2_[1] (in view view:work.TinyFPGA_EX(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@W:MO129:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | Sequential instance tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.genblk1[2].ep_state_2_[0] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO197:@XP_HELP">MO197</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\common\usb_fs_in_pe.v:221:6:221:12:@W:MO197:@XP_MSG">usb_fs_in_pe.v(221)</a><!@TM:1520378969> | Removing FSM register tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.genblk1\[2\]\.ep_state_2_[0] (in view view:work.TinyFPGA_EX(verilog)) because its output is a constant.</font>

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 181MB)

@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1520378969> | Automatically generated clock usb_pll_inst|CLKOP_inferred_clock is not used and is being removed 
@N:<a href="@N:MT617:@XP_HELP">MT617</a> : <!@TM:1520378969> | Automatically generated clock usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s|in_xfr_state_derived_clock[1] has lost its master clock usb_pll_inst|CLKOP_inferred_clock and is being removed 
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1520378969> | Automatically generated clock usb_fs_in_pe_3_32s_0s_1s_2s_3s_0s_1s_2s_3s|in_xfr_state_derived_clock[1] is not used and is being removed 


@S |Clock Optimization Summary


<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 10 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 505 clock pin(s) of sequential element(s)
0 instances converted, 505 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|S:pin_clk@|E:boot_delay[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       pin_clk             port                   10         boot_delay[0]  
=======================================================================================
================================================================================================================= Gated/Generated Clocks =================================================================================================================
Clock Tree ID     Driving Element                 Drive Element Type     Fanout     Sample Instance                         Explanation                                                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|S:usb_pll_inst_inst.PLLInst_0@|E:tinyfpga_bootloader_inst.count_down@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       usb_pll_inst_inst.PLLInst_0     EHXPLLL                505        tinyfpga_bootloader_inst.count_down     Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
==========================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 143MB peak: 181MB)

Writing Analyst data base C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\synwork\diamond_impl_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 177MB peak: 181MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1520378969> | Writing EDF file: C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl.edi 
L-2016.09L
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1520378969> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 184MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 179MB peak: 184MB)

<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\boards\tinyfpga_ex\bootloader.v:93:10:93:22:@W:MT246:@XP_MSG">bootloader.v(93)</a><!@TM:1520378969> | Blackbox USRMCLK is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="c:\users\lvale\documents\tinyfpga\repos\tinyfpga-bootloader\boards\tinyfpga_ex\impl\source\usb_pll_inst.v:54:12:54:21:@W:MT246:@XP_MSG">usb_pll_inst.v(54)</a><!@TM:1520378969> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1520378969> | Found inferred clock TinyFPGA_EX|pin_clk with period 2.28ns. Please declare a user-defined clock on object "p:pin_clk"</font> 


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Tue Mar 06 15:29:29 2018
#


Top view:               TinyFPGA_EX
Requested Frequency:    437.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1520378969> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1520378969> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary10></a>Performance Summary</a>
*******************


Worst slack in design: -0.994

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
TinyFPGA_EX|pin_clk     437.8 MHz     372.1 MHz     2.284         2.688         -0.403     inferred     Autoconstr_clkgroup_0
System                  177.5 MHz     150.9 MHz     5.633         6.627         -0.994     system       system_clkgroup      
=============================================================================================================================





<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               System               |  5.633       -0.994  |  No paths    -      |  No paths    -      |  No paths    -    
System               TinyFPGA_EX|pin_clk  |  2.284       -0.109  |  No paths    -      |  No paths    -      |  No paths    -    
TinyFPGA_EX|pin_clk  TinyFPGA_EX|pin_clk  |  2.284       -0.403  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport13></a>Detailed Report for Clock: TinyFPGA_EX|pin_clk</a>
====================================



<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************

                  Starting                                                      Arrival           
Instance          Reference               Type        Pin     Net               Time        Slack 
                  Clock                                                                           
--------------------------------------------------------------------------------------------------
boot_delay[0]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[0]     0.853       -0.403
boot_delay[1]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[1]     0.853       -0.342
boot_delay[2]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[2]     0.853       -0.342
boot_delay[3]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[3]     0.853       -0.281
boot_delay[4]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[4]     0.853       -0.281
boot_delay[5]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[5]     0.853       -0.220
boot_delay[6]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[6]     0.853       -0.220
boot_delay[8]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[8]     0.907       0.546 
boot_delay[7]     TinyFPGA_EX|pin_clk     FD1P3AX     Q       boot_delay[7]     0.853       0.600 
initiate_boot     TinyFPGA_EX|pin_clk     FD1S3AX     Q       initiate_boot     1.048       0.792 
==================================================================================================


<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************

                  Starting                                                        Required           
Instance          Reference               Type        Pin     Net                 Time         Slack 
                  Clock                                                                              
-----------------------------------------------------------------------------------------------------
boot_delay[7]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[7]     2.230        -0.403
boot_delay[8]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[8]     2.230        -0.403
boot_delay[5]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[5]     2.230        -0.342
boot_delay[6]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[6]     2.230        -0.342
boot_delay[3]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[3]     2.230        -0.281
boot_delay[4]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[4]     2.230        -0.281
boot_delay[1]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[1]     2.230        -0.220
boot_delay[2]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[2]     2.230        -0.220
boot_delay[0]     TinyFPGA_EX|pin_clk     FD1P3AX     D       boot_delay_s[0]     2.230        0.600 
initiate_boot     TinyFPGA_EX|pin_clk     FD1S3AX     D       N_14603_0           2.230        0.792 
=====================================================================================================



<a name=worstPaths16></a>Worst Path Information</a>
<a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl.srr:srsfC:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl.srs:fp:110878:112444:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      2.284
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.230

    - Propagation time:                      2.634
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.403

    Number of logic level(s):                5
    Starting point:                          boot_delay[0] / Q
    Ending point:                            boot_delay[8] / D
    The start point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK
    The end   point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                    Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
boot_delay[0]           FD1P3AX     Q        Out     0.853     0.853       -         
boot_delay[0]           Net         -        -       -         -           1         
boot_delay_cry_0[0]     CCU2C       A1       In      0.000     0.853       -         
boot_delay_cry_0[0]     CCU2C       COUT     Out     0.900     1.753       -         
boot_delay_cry[0]       Net         -        -       -         -           1         
boot_delay_cry_0[1]     CCU2C       CIN      In      0.000     1.753       -         
boot_delay_cry_0[1]     CCU2C       COUT     Out     0.061     1.814       -         
boot_delay_cry[2]       Net         -        -       -         -           1         
boot_delay_cry_0[3]     CCU2C       CIN      In      0.000     1.814       -         
boot_delay_cry_0[3]     CCU2C       COUT     Out     0.061     1.875       -         
boot_delay_cry[4]       Net         -        -       -         -           1         
boot_delay_cry_0[5]     CCU2C       CIN      In      0.000     1.875       -         
boot_delay_cry_0[5]     CCU2C       COUT     Out     0.061     1.936       -         
boot_delay_cry[6]       Net         -        -       -         -           1         
boot_delay_cry_0[7]     CCU2C       CIN      In      0.000     1.936       -         
boot_delay_cry_0[7]     CCU2C       S1       Out     0.698     2.634       -         
boot_delay_s[8]         Net         -        -       -         -           1         
boot_delay[8]           FD1P3AX     D        In      0.000     2.634       -         
=====================================================================================


Path information for path number 2: 
      Requested Period:                      2.284
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.230

    - Propagation time:                      2.634
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.403

    Number of logic level(s):                5
    Starting point:                          boot_delay[0] / Q
    Ending point:                            boot_delay[7] / D
    The start point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK
    The end   point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                    Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
boot_delay[0]           FD1P3AX     Q        Out     0.853     0.853       -         
boot_delay[0]           Net         -        -       -         -           1         
boot_delay_cry_0[0]     CCU2C       A1       In      0.000     0.853       -         
boot_delay_cry_0[0]     CCU2C       COUT     Out     0.900     1.753       -         
boot_delay_cry[0]       Net         -        -       -         -           1         
boot_delay_cry_0[1]     CCU2C       CIN      In      0.000     1.753       -         
boot_delay_cry_0[1]     CCU2C       COUT     Out     0.061     1.814       -         
boot_delay_cry[2]       Net         -        -       -         -           1         
boot_delay_cry_0[3]     CCU2C       CIN      In      0.000     1.814       -         
boot_delay_cry_0[3]     CCU2C       COUT     Out     0.061     1.875       -         
boot_delay_cry[4]       Net         -        -       -         -           1         
boot_delay_cry_0[5]     CCU2C       CIN      In      0.000     1.875       -         
boot_delay_cry_0[5]     CCU2C       COUT     Out     0.061     1.936       -         
boot_delay_cry[6]       Net         -        -       -         -           1         
boot_delay_cry_0[7]     CCU2C       CIN      In      0.000     1.936       -         
boot_delay_cry_0[7]     CCU2C       S0       Out     0.698     2.634       -         
boot_delay_s[7]         Net         -        -       -         -           1         
boot_delay[7]           FD1P3AX     D        In      0.000     2.634       -         
=====================================================================================


Path information for path number 3: 
      Requested Period:                      2.284
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.230

    - Propagation time:                      2.572
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.342

    Number of logic level(s):                4
    Starting point:                          boot_delay[1] / Q
    Ending point:                            boot_delay[8] / D
    The start point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK
    The end   point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                    Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
boot_delay[1]           FD1P3AX     Q        Out     0.853     0.853       -         
boot_delay[1]           Net         -        -       -         -           1         
boot_delay_cry_0[1]     CCU2C       A0       In      0.000     0.853       -         
boot_delay_cry_0[1]     CCU2C       COUT     Out     0.900     1.753       -         
boot_delay_cry[2]       Net         -        -       -         -           1         
boot_delay_cry_0[3]     CCU2C       CIN      In      0.000     1.753       -         
boot_delay_cry_0[3]     CCU2C       COUT     Out     0.061     1.814       -         
boot_delay_cry[4]       Net         -        -       -         -           1         
boot_delay_cry_0[5]     CCU2C       CIN      In      0.000     1.814       -         
boot_delay_cry_0[5]     CCU2C       COUT     Out     0.061     1.875       -         
boot_delay_cry[6]       Net         -        -       -         -           1         
boot_delay_cry_0[7]     CCU2C       CIN      In      0.000     1.875       -         
boot_delay_cry_0[7]     CCU2C       S1       Out     0.698     2.572       -         
boot_delay_s[8]         Net         -        -       -         -           1         
boot_delay[8]           FD1P3AX     D        In      0.000     2.572       -         
=====================================================================================


Path information for path number 4: 
      Requested Period:                      2.284
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.230

    - Propagation time:                      2.572
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.342

    Number of logic level(s):                4
    Starting point:                          boot_delay[2] / Q
    Ending point:                            boot_delay[8] / D
    The start point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK
    The end   point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                    Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
boot_delay[2]           FD1P3AX     Q        Out     0.853     0.853       -         
boot_delay[2]           Net         -        -       -         -           1         
boot_delay_cry_0[1]     CCU2C       A1       In      0.000     0.853       -         
boot_delay_cry_0[1]     CCU2C       COUT     Out     0.900     1.753       -         
boot_delay_cry[2]       Net         -        -       -         -           1         
boot_delay_cry_0[3]     CCU2C       CIN      In      0.000     1.753       -         
boot_delay_cry_0[3]     CCU2C       COUT     Out     0.061     1.814       -         
boot_delay_cry[4]       Net         -        -       -         -           1         
boot_delay_cry_0[5]     CCU2C       CIN      In      0.000     1.814       -         
boot_delay_cry_0[5]     CCU2C       COUT     Out     0.061     1.875       -         
boot_delay_cry[6]       Net         -        -       -         -           1         
boot_delay_cry_0[7]     CCU2C       CIN      In      0.000     1.875       -         
boot_delay_cry_0[7]     CCU2C       S1       Out     0.698     2.572       -         
boot_delay_s[8]         Net         -        -       -         -           1         
boot_delay[8]           FD1P3AX     D        In      0.000     2.572       -         
=====================================================================================


Path information for path number 5: 
      Requested Period:                      2.284
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.230

    - Propagation time:                      2.572
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.342

    Number of logic level(s):                4
    Starting point:                          boot_delay[0] / Q
    Ending point:                            boot_delay[5] / D
    The start point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK
    The end   point is clocked by            TinyFPGA_EX|pin_clk [rising] on pin CK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                    Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
boot_delay[0]           FD1P3AX     Q        Out     0.853     0.853       -         
boot_delay[0]           Net         -        -       -         -           1         
boot_delay_cry_0[0]     CCU2C       A1       In      0.000     0.853       -         
boot_delay_cry_0[0]     CCU2C       COUT     Out     0.900     1.753       -         
boot_delay_cry[0]       Net         -        -       -         -           1         
boot_delay_cry_0[1]     CCU2C       CIN      In      0.000     1.753       -         
boot_delay_cry_0[1]     CCU2C       COUT     Out     0.061     1.814       -         
boot_delay_cry[2]       Net         -        -       -         -           1         
boot_delay_cry_0[3]     CCU2C       CIN      In      0.000     1.814       -         
boot_delay_cry_0[3]     CCU2C       COUT     Out     0.061     1.875       -         
boot_delay_cry[4]       Net         -        -       -         -           1         
boot_delay_cry_0[5]     CCU2C       CIN      In      0.000     1.875       -         
boot_delay_cry_0[5]     CCU2C       S0       Out     0.698     2.572       -         
boot_delay_s[5]         Net         -        -       -         -           1         
boot_delay[5]           FD1P3AX     D        In      0.000     2.572       -         
=====================================================================================




====================================
<a name=clockReport17></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack18></a>Starting Points with Worst Slack</a>
********************************

                                                                                   Starting                                                   Arrival           
Instance                                                                           Reference     Type        Pin     Net                      Time        Slack 
                                                                                   Clock                                                                        
----------------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]     System        FD1S3AX     Q       current_endp_fast[0]     0.955       -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[0\][0]      System        FD1P3IX     Q       ep_get_addr\[0\][0]      0.853       -0.892
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[1\][0]      System        FD1P3IX     Q       ep_get_addr\[1\][0]      0.853       -0.892
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_0_rep1      System        FD1S3AX     Q       current_endp_0_rep1      0.985       -0.861
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[0\][1]      System        FD1P3IX     Q       ep_get_addr\[0\][1]      0.853       -0.732
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[1\][1]      System        FD1P3IX     Q       ep_get_addr\[1\][1]      0.853       -0.732
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[0\][2]      System        FD1P3IX     Q       ep_get_addr\[0\][2]      0.853       -0.729
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[1\][2]      System        FD1P3IX     Q       ep_get_addr\[1\][2]      0.853       -0.729
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[0\][4]      System        FD1P3IX     Q       ep_get_addr\[0\][4]      0.853       -0.683
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_get_addr\[1\][4]      System        FD1P3IX     Q       ep_get_addr\[1\][4]      0.853       -0.683
================================================================================================================================================================


<a name=endingSlack19></a>Ending Points with Worst Slack</a>
******************************

                                                                             Starting                                                   Required           
Instance                                                                     Reference     Type        Pin     Net                      Time         Slack 
                                                                             Clock                                                                         
-----------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[1]     System        FD1S3AX     D       data_shift_reg_15[1]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[2]     System        FD1S3AX     D       data_shift_reg_15[2]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[3]     System        FD1S3AX     D       data_shift_reg_15[3]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[4]     System        FD1S3AX     D       data_shift_reg_15[4]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[5]     System        FD1S3AX     D       data_shift_reg_15[5]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[6]     System        FD1S3AX     D       data_shift_reg_15[6]     5.579        -0.994
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[0]     System        FD1S3AX     D       data_shift_reg_15[0]     5.579        -0.591
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[7]     System        FD1S3AX     D       data_shift_reg_15[7]     5.579        -0.591
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state[1]          System        FD1P3AX     D       pkt_state_cnst[1]        5.579        -0.531
tinyfpga_bootloader_inst.usb_spi_bridge_ep_inst.spi_state[2]                 System        FD1S3AX     D       spi_state_next[2]        5.579        -0.503
===========================================================================================================================================================



<a name=worstPaths20></a>Worst Path Information</a>
<a href="C:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl.srr:srsfC:\Users\lvale\Documents\TinyFPGA\repos\TinyFPGA-Bootloader\boards\TinyFPGA_EX\impl\diamond_impl.srs:fp:129044:134060:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.633
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.579

    - Propagation time:                      6.572
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -0.994

    Number of logic level(s):                10
    Starting point:                          tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0] / Q
    Ending point:                            tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[1] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]          FD1S3AX      Q        Out     0.955     0.955       -         
current_endp_fast[0]                                                                    Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     A        In      0.000     0.955       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     Z        Out     0.708     1.663       -         
N_165                                                                                   Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     A        In      0.000     1.663       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     Z        Out     0.819     2.482       -         
un16_ep_get_addr[0]                                                                     Net          -        -       -         -           14        
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        C1       In      0.000     2.482       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        COUT     Out     0.900     3.382       -         
more_data_to_send_cry_0                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        CIN      In      0.000     3.382       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        COUT     Out     0.061     3.443       -         
more_data_to_send_cry_2                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        CIN      In      0.000     3.443       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        COUT     Out     0.061     3.504       -         
more_data_to_send_cry_4                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        CIN      In      0.000     3.504       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        S1       Out     0.872     4.375       -         
more_data_to_send                                                                       Net          -        -       -         -           7         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     C        In      0.000     4.375       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     Z        Out     0.798     5.173       -         
data_shift_reg_1_sqmuxa                                                                 Net          -        -       -         -           9         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[1]          ORCALUT4     C        In      0.000     5.173       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[1]          ORCALUT4     Z        Out     0.606     5.779       -         
data_shift_reg_11_bm[1]                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[1]             PFUMX        ALUT     In      0.000     5.779       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[1]             PFUMX        Z        Out     0.403     6.183       -         
data_shift_reg_11[1]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[1]            ORCALUT4     D        In      0.000     6.183       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[1]            ORCALUT4     Z        Out     0.390     6.572       -         
data_shift_reg_15[1]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[1]                FD1S3AX      D        In      0.000     6.572       -         
======================================================================================================================================================


Path information for path number 2: 
      Requested Period:                      5.633
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.579

    - Propagation time:                      6.572
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -0.994

    Number of logic level(s):                10
    Starting point:                          tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0] / Q
    Ending point:                            tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[6] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]          FD1S3AX      Q        Out     0.955     0.955       -         
current_endp_fast[0]                                                                    Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     A        In      0.000     0.955       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     Z        Out     0.708     1.663       -         
N_165                                                                                   Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     A        In      0.000     1.663       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     Z        Out     0.819     2.482       -         
un16_ep_get_addr[0]                                                                     Net          -        -       -         -           14        
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        C1       In      0.000     2.482       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        COUT     Out     0.900     3.382       -         
more_data_to_send_cry_0                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        CIN      In      0.000     3.382       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        COUT     Out     0.061     3.443       -         
more_data_to_send_cry_2                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        CIN      In      0.000     3.443       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        COUT     Out     0.061     3.504       -         
more_data_to_send_cry_4                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        CIN      In      0.000     3.504       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        S1       Out     0.872     4.375       -         
more_data_to_send                                                                       Net          -        -       -         -           7         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     C        In      0.000     4.375       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     Z        Out     0.798     5.173       -         
data_shift_reg_1_sqmuxa                                                                 Net          -        -       -         -           9         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[6]          ORCALUT4     C        In      0.000     5.173       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[6]          ORCALUT4     Z        Out     0.606     5.779       -         
data_shift_reg_11_bm[6]                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[6]             PFUMX        ALUT     In      0.000     5.779       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[6]             PFUMX        Z        Out     0.403     6.183       -         
data_shift_reg_11[6]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[6]            ORCALUT4     D        In      0.000     6.183       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[6]            ORCALUT4     Z        Out     0.390     6.572       -         
data_shift_reg_15[6]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[6]                FD1S3AX      D        In      0.000     6.572       -         
======================================================================================================================================================


Path information for path number 3: 
      Requested Period:                      5.633
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.579

    - Propagation time:                      6.572
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -0.994

    Number of logic level(s):                10
    Starting point:                          tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0] / Q
    Ending point:                            tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[5] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]          FD1S3AX      Q        Out     0.955     0.955       -         
current_endp_fast[0]                                                                    Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     A        In      0.000     0.955       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     Z        Out     0.708     1.663       -         
N_165                                                                                   Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     A        In      0.000     1.663       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     Z        Out     0.819     2.482       -         
un16_ep_get_addr[0]                                                                     Net          -        -       -         -           14        
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        C1       In      0.000     2.482       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        COUT     Out     0.900     3.382       -         
more_data_to_send_cry_0                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        CIN      In      0.000     3.382       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        COUT     Out     0.061     3.443       -         
more_data_to_send_cry_2                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        CIN      In      0.000     3.443       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        COUT     Out     0.061     3.504       -         
more_data_to_send_cry_4                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        CIN      In      0.000     3.504       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        S1       Out     0.872     4.375       -         
more_data_to_send                                                                       Net          -        -       -         -           7         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     C        In      0.000     4.375       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     Z        Out     0.798     5.173       -         
data_shift_reg_1_sqmuxa                                                                 Net          -        -       -         -           9         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[5]          ORCALUT4     C        In      0.000     5.173       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[5]          ORCALUT4     Z        Out     0.606     5.779       -         
data_shift_reg_11_bm[5]                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[5]             PFUMX        ALUT     In      0.000     5.779       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[5]             PFUMX        Z        Out     0.403     6.183       -         
data_shift_reg_11[5]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[5]            ORCALUT4     D        In      0.000     6.183       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[5]            ORCALUT4     Z        Out     0.390     6.572       -         
data_shift_reg_15[5]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[5]                FD1S3AX      D        In      0.000     6.572       -         
======================================================================================================================================================


Path information for path number 4: 
      Requested Period:                      5.633
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.579

    - Propagation time:                      6.572
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -0.994

    Number of logic level(s):                10
    Starting point:                          tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0] / Q
    Ending point:                            tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[4] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]          FD1S3AX      Q        Out     0.955     0.955       -         
current_endp_fast[0]                                                                    Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     A        In      0.000     0.955       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     Z        Out     0.708     1.663       -         
N_165                                                                                   Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     A        In      0.000     1.663       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     Z        Out     0.819     2.482       -         
un16_ep_get_addr[0]                                                                     Net          -        -       -         -           14        
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        C1       In      0.000     2.482       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        COUT     Out     0.900     3.382       -         
more_data_to_send_cry_0                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        CIN      In      0.000     3.382       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        COUT     Out     0.061     3.443       -         
more_data_to_send_cry_2                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        CIN      In      0.000     3.443       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        COUT     Out     0.061     3.504       -         
more_data_to_send_cry_4                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        CIN      In      0.000     3.504       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        S1       Out     0.872     4.375       -         
more_data_to_send                                                                       Net          -        -       -         -           7         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     C        In      0.000     4.375       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     Z        Out     0.798     5.173       -         
data_shift_reg_1_sqmuxa                                                                 Net          -        -       -         -           9         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[4]          ORCALUT4     C        In      0.000     5.173       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[4]          ORCALUT4     Z        Out     0.606     5.779       -         
data_shift_reg_11_bm[4]                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[4]             PFUMX        ALUT     In      0.000     5.779       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[4]             PFUMX        Z        Out     0.403     6.183       -         
data_shift_reg_11[4]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[4]            ORCALUT4     D        In      0.000     6.183       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[4]            ORCALUT4     Z        Out     0.390     6.572       -         
data_shift_reg_15[4]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[4]                FD1S3AX      D        In      0.000     6.572       -         
======================================================================================================================================================


Path information for path number 5: 
      Requested Period:                      5.633
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         5.579

    - Propagation time:                      6.572
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     -0.994

    Number of logic level(s):                10
    Starting point:                          tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0] / Q
    Ending point:                            tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[3] / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.current_endp_fast[0]          FD1S3AX      Q        Out     0.955     0.955       -         
current_endp_fast[0]                                                                    Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     A        In      0.000     0.955       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr_0[0]         ORCALUT4     Z        Out     0.708     1.663       -         
N_165                                                                                   Net          -        -       -         -           3         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     A        In      0.000     1.663       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.un16_ep_get_addr[0]           ORCALUT4     Z        Out     0.819     2.482       -         
un16_ep_get_addr[0]                                                                     Net          -        -       -         -           14        
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        C1       In      0.000     2.482       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_0_0     CCU2C        COUT     Out     0.900     3.382       -         
more_data_to_send_cry_0                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        CIN      In      0.000     3.382       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_1_0     CCU2C        COUT     Out     0.061     3.443       -         
more_data_to_send_cry_2                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        CIN      In      0.000     3.443       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_3_0     CCU2C        COUT     Out     0.061     3.504       -         
more_data_to_send_cry_4                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        CIN      In      0.000     3.504       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_in_pe_inst.more_data_to_send_cry_5_0     CCU2C        S1       Out     0.872     4.375       -         
more_data_to_send                                                                       Net          -        -       -         -           7         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     C        In      0.000     4.375       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.pkt_state_RNIPEMH1[0]            ORCALUT4     Z        Out     0.798     5.173       -         
data_shift_reg_1_sqmuxa                                                                 Net          -        -       -         -           9         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[3]          ORCALUT4     C        In      0.000     5.173       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11_bm[3]          ORCALUT4     Z        Out     0.606     5.779       -         
data_shift_reg_11_bm[3]                                                                 Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[3]             PFUMX        ALUT     In      0.000     5.779       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_11[3]             PFUMX        Z        Out     0.403     6.183       -         
data_shift_reg_11[3]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[3]            ORCALUT4     D        In      0.000     6.183       -         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg_RNO[3]            ORCALUT4     Z        Out     0.390     6.572       -         
data_shift_reg_15[3]                                                                    Net          -        -       -         -           1         
tinyfpga_bootloader_inst.usb_fs_pe_inst.usb_fs_tx_inst.data_shift_reg[3]                FD1S3AX      D        In      0.000     6.572       -         
======================================================================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 179MB peak: 184MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 179MB peak: 184MB)

---------------------------------------
<a name=resourceUsage21></a>Resource Usage Report</a>
Part: lfe5u_45f-6

Register bits: 497 of 43848 (1%)
PIC Latch:       0
I/O cells:       11


Details:
BB:             2
CCU2C:          100
DPR16X4C:       18
EHXPLLL:        1
FD1P3AX:        248
FD1P3IX:        18
FD1P3JX:        8
FD1S3AX:        131
FD1S3AY:        1
FD1S3IX:        86
FD1S3JX:        3
GSR:            1
IB:             2
IFS1P3DX:       1
INV:            4
OB:             7
OFS1P3DX:       1
ORCALUT4:       840
PFUMX:          28
PUR:            1
ROM16X1A:       2
ROM32X1A:       4
ROM64X1A:       8
USRMCLK:        1
VHI:            11
VLO:            3
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 38MB peak: 184MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Tue Mar 06 15:29:29 2018

###########################################################]

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